{"title":"A Test Model for Hardware and Software","authors":"J. Sziray","doi":"10.1109/PRDC.2011.41","DOIUrl":null,"url":null,"abstract":"The paper presents a unified test model which is a mapping scheme for describing the one-to-one correspondence between the input and output domains of a given hardware or software system. Here the test inputs and the fault classes are also involved. The test model incorporates both the verification and the validation schemes for the hardware and software.","PeriodicalId":254760,"journal":{"name":"2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRDC.2011.41","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper presents a unified test model which is a mapping scheme for describing the one-to-one correspondence between the input and output domains of a given hardware or software system. Here the test inputs and the fault classes are also involved. The test model incorporates both the verification and the validation schemes for the hardware and software.
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