A SoPC FPGA Implementing of an Enhanced Parallel CFAR Architecture

Abstract

This paper presents a practical experience in designing a programmable system-on-chip for a complex and modern purpose associated with high-resolution, real-time target detection for radar systems. In this paper, an embedded architecture that merges into a single platform, the two hardware and software components. This architecture is implemented using a PC board based on a field programmable gate array (FPGA). The technique used for the detection process is the automatic censored ordered statistics detection (ACOSD) CFAR with the shared resource technique. All of which we exploit the robustness of the hardware that operates two ACOSD detector in parallel, alongside the flexibility of the software based on a microprocessor ARM Cortex A9. The hardware/software embedded system detector is developed using Xilinx Vivado high-level synthesis and Xilinx SDK. The new Hardware/Software design has been uploaded onto the Zedboard Zynq 7000 FPGA board. The design operates at a maximum frequency of 148 MHz and performs real-time target detection with an execution time of 0.24 μs, which is lower than 0.5 μs of the critical time required for high-resolution target detection.