Systolic architectures for decoding Reed-Solomon codes

[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI:10.1109/ASAP.1990.145444

J. Nelson, Arifur Rahman, E. McQuade

引用次数: 1

Abstract

A systolic implementation of a Reed-Solomon decoder is presented which with minor modification is suitable for BCH and Goppa codes. The various operations involved in decoding such codes were analyzed and the results are described. Systolic array architectures are derived for the various steps including the syndrome calculation, key equation solution and error evaluation. Since the throughput of the decoder is effectively determined by the speed of the multipliers, various multiplier architectures are discussed briefly. The architectures presented improve upon previous designs. The result is highly regular and modular, and thus it is more suitable for VLSI implementation.<>

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用于解码里德-所罗门码的系统架构

本文介绍了一种里德-所罗门解码器的系统实现方法，稍加修改后即可用于 BCH 和 Goppa 编码。对解码这类编码所涉及的各种操作进行了分析，并对结果进行了描述。为包括综合征计算、键方程求解和误差评估在内的各个步骤推导出了收缩阵列架构。由于解码器的吞吐量实际上取决于乘法器的速度，因此简要讨论了各种乘法器架构。所介绍的架构改进了以前的设计。其结果是高度规则化和模块化的，因此更适合于 VLSI 实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1990] Proceedings of the International Conference on Application Specific Array Processors

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