Design issues for flip-chip ICs in multilayer packages

Abstract

Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.