The TLB slice-a low-cost high-speed address translation mechanism

Abstract

The MIPS R6000 microprocessor relies on a new type of translation lookaside buffer, called a TLB slice, which is less than one-tenth the size of a conventional TLB and as fast as one multiplexer delay, yet has a high enough hit rate to be practical. The fast translation makes it possible to use a physical cache without adding a translation stage to the processor's pipeline. The small size makes it possible to include address translation on-chip, even in a technology with a limited number of devices. The key idea behind the TLB slice is to have both a virtual tag and a physical tag on a physically indexed cache.<>