A VLSI implementation of an adaptive genetic algorithm processor

Abstract

A genetic algorithm (GA) is a powerful heuristic method of selection based on natural living process. Because of larger size of the scheduling, implementing GA in software was tiresome and highly time complex. GA processor parallelizes the work in order to reduce the processing time and increases the speed, but still the efficiency of the GA is maintained through quality solutions. This work proposes a fast Adaptive Genetic Algorithm Processor (AGAP) for the implementation of Adaptive Noise Cancelation (ANC) filters in VLSI. The AGAP updates the coefficients of the ANC filter nullifying the effect of noise at the output end. The coefficients are optimized at every stage of the algorithm and are adaptively changed in order to meet the constraints of active noise canceller. AGAP processor is modeled using Verilog HDL in Xilinx ISE 14.6 platform. The functional performance of each module and the processor are simulated for their correctness to be synthesized using Spartan 6 XC6SLX45-3CSG324I FPGA.