Method for the diagonosis of a single intermittent fault in combinatorial logic circuits

Abstract

The paper presents a technique, based on probability theory, which detects a well behaved intermittent fault in combinatorial logic circuits. The procedure employs repeated applications of tests that detect solid faults in the circuit. The time period, during which a test is repeatedly applied, depends on the probability of detection desired and is derived from the Poisson distribution of statistics. The percentage of faults located using repeated tests via software simulation agrees very well with the statistical prediction.