A Power Efficient Approach to Fault-Tolerant Register File Design

Abstract

Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: single error correction (SEC) Hamming code, duplication with parity, and triple modular redundancy (TMR). As a case study, this approach is implemented on the register file of an OpenRISC 1200 processor. The experimental calculation of the power consumption shows that the proposed approach saves about 67%, 62%, and 58% power for TMR, duplication with parity, and SEC Hamming code, respectively.