A Quick Algorithm Implementation Method for ARM-FPGA Integrated SDR Platform

Abstract

A new design method for radio communication algorithm verification is presented in this paper. When developing communication algorithm on Field-Programmable Gate Array (FPGA) based Software Defined Radio (SDR) system, traditional steps include the algorithm simulation, FPGA synthesis and implementations, hardware validation and iterative adjustment. In general, the algorithm simulation step is entirely isolated with hardware environment. More pressures are added on hardware debug process and this will lead to a longer production period. New generation of FPGA products consists of both ARM hard cores and FPGA arrays. Due to its existence of ARM core, data acquiring system is easy to be built. When developing algorithm and optimizing parameters, data could be obtained directly from hardware and be simulated on computer in real time. The algorithm could be directly verified on hardware environment without building FPGA model. Therefore, algorithm developing process could be accelerated.