A 0.18 pJ/Conversion Step Hybrid Structure based ADC

Dipti, Shipra Gaur, Kavindra Kandpal, P. K. Misra, M. Goswami
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Abstract

This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate remaining 2 bits. With this hybrid configuration, the ADC consumes 12.8mW of power and sampling rate of 533 MSPS when operated at 1.8V.
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基于0.18 pJ/转换阶跃混合结构的ADC
本文提出了一种8位ADC的混合设计,该设计结合了用于节省面积的二进制搜索ADC和用于提高运算速度的闪存ADC。该ADC架构分为两个阶段:第一阶段使用二分搜索拓扑进行设计,第二阶段使用flash架构进行设计。二进制查找阶段设置为仅生成6位,而闪存阶段设置为生成剩余的2位。采用这种混合配置,当工作在1.8V时,ADC功耗为12.8mW,采样率为533 MSPS。
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