Hardware-Software Cosynthesis of Multiprocessor Embedded Architectures

Abstract

Hardware software cosynthesis process tries to determine system architecture for an embedded application. In this paper, a new cosynthesis approach is presented, which targets distributed memory architectures for high performance embedded systems. The target embedded architecture consists of heterogeneous processing elements (PEs) with point- to-point communication structure. The main steps of the cosynthesis process include PE selection, pipelined task allocation and scheduling, and regular topology mapping. Initially, an irregular topology is generated and then mapped to regular topology architecture (e.g. mesh, hypercube and tree). The cosynthesis method is tested for the MPEG encoder application.