Search Algorithm for Optimal Synthesis of Decoder for RAMs with Error-Correcting Codes

Abstract

This paper addresses the issue of optimal design of the decoder in fault-tolerant RAMs with Single Error Correcting and Double Error Detecting facilities (SECDED). If for the encoding logic it is recommended to generate each control bit independently (a classic implementation), for the decoding logic the authors recommend a simpler synthesis, in order to reduce the complexity as much as possible. This is explained by the fact that the decoding logic no longer has any fault tolerance facilities. Since the decoder is implemented as a network of XOR logic gates, the problem we address is to find the simplest structure using 2-input or 3-input XOR gates as base cells. To this end, a search algorithm has been implemented to identify in the parity-check matrix common sets of bits that can be used to generate multiple error control bits. The efficiency of the solution we propose, in terms of complexity, is demonstrated by comparison with the classic one in which the error bits are generated independently.