Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems

Abstract

Thanks to their dynamic reconfiguration capabilities, FPGAs are used in application domains ranging from embedded systems to high performance computing. Nevertheless, as FPGAs usually rely on SRAM memories to keep their current configuration, they are highly sensitive to radiation. The robustness of FPGA-based implementations can be improved by tuning the configuration parameters of selected IP cores or EDA tools. As many different parameters can usually be set at several configuration levels, this constitutes a huge design space to be explored. Accordingly, not only suitable techniques are required to sample as many different configurations as possible, but also novel fault injection approaches are necessary to reduce the number of faults to be injected and speed up as much as possible the experimentation as a whole. To accomplish this goal, this paper integrates state of the art FPGA-based approaches to speed up the execution of individual fault injection experiments with a novel proposal that minimises the number of fault injection experiments required to successfully explore the design space with robustness in mind and following a genetic algorithm. This approach is exemplified by tuning the Vivado Design Suite to optimize the robustness and clock frequency of MC8051, AVR, and Microblaze soft-core processors.