Automated analog IC design constraints generation for a layout-aware sizing approach

Abstract

This paper presents an approach to automatically generate circuit-level design constraints to a layout-aware sizing approach. The proposed approach is an enhanced version and implementation of an established method, based on pattern recognition and symmetry detection, and is integrated in the AIDAsoft electronic design automation (EDA) environment. The generation of constraints increases the automation of the design process and reduces the risk of errors, assisting the project designer during the design specification setup. The validity and effectiveness of the proposed approach is illustrated for the synthesis of classical circuit structures in the AIDAsoft environment.