A new DRAM architecture and its control method for the system power consumption

Abstract

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a re-write operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. According to a new proposed method the refresh operation frequency and its power consumption reduce to 1/(2 to the Nth) (N=1, 2, 3, 4) when full memory capacity is not required, by effectively extending the refresh operation interval. The proposal includes the conversion from 1 cell/bit to (2 to the Nth) cells/bit, which reduces the variation of retention times among memory cells. This leads the refresh operation frequency from 1/(2 to the Nth) to 1/(2 to the Nth) X 1/(2 to the Nth), while it accompanies the additional charging power for the composed memory cell. A system can select the best way of 1 cell/bit and (2 to the Nth) cells/bit from the total viewpoint, while all conventional functions and operations in the full array access mode are fully compatible.