A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression

Abstract

Long test application time for a System on Chip (SoC) is a major problem in digital design testing. This problem mostly originates from large test data. High volume test data not only increases required ATE memory and bandwidth, but also increases test time. Test compression reduces test data volume without any impact on its coverage. This work proposes two novel efficient test data compression schemes. These schemes suggest a slice partitioning along with a multiple dictionaries bitmask approach, and also a slice bit reordering method. These approaches are combined with low power method to decrease power consumption without sacrificing compression efficiency. Experimental results show improvements in compression efficiency and power consumption when compared with the existing works.