A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation

Abstract

The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account since the early phases of a complex system-on-chip (SoC) design. Transaction level models for SoC are gaining increasing attention with emerging architectural modeling standards like SystemC. In this paper a transaction level modeling of asynchronous network-on-chip (NOC) architecture is presented. This modeling enables early system-level validation of circuit as well as energy evaluation of circuit, which will have important impact on high-level design decisions.