Signal integrity analysis of through-silicon via based 3D integrated circuit

Abstract

This paper presents an accurate compact scalable RLCG (Resistance, Inductance, Capacitance, and Conductance) model for electrical modeling of through-silicon vias in 3D IC packaging. Closed-form formulas for R and L are derived by full-wave approach, while C and G are taken from static solutions. The equivalent circuit model can capture almost all the parasitic effects, such as skin, proximity and MOS capacitance effect of through-silicon vias and the effect of lossy silicon. Therefore, it yields accurate results comparable to the full-wave solver.