An Enhanced Dynamic Switch Logic with Floating-Gate MOS Transistors

Abstract

A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically simplified by utilizing multiple-input FGMOS transistors. The proposed dynamic logic does not require complementary inputs, and keeps the benefits of EDCVSL. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is given. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits.