A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI:10.1109/ASPDAC.2011.5722306

J. Furuta, C. Hamanaka, Kazutoshi Kobayashi, H. Onodera

引用次数: 8

Abstract

We fabricated a 65nm LSI including flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. It consists of two FF arrays as follows. One is an array composed of redundant FFs to confirm radiation hardness of the proposed and conventional redundant FFs. The other is an array composed of conventional D-FFs to measure SEU (Single Event Upset) and MCU(Multiple Cell Upset) by the distance from tap cells.

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一种65nm触发器阵列，用于测量对高能中子和α粒子的软错误弹性

我们制作了一个包含触发器阵列的65nm大规模集成电路，用于测量高能中子和α粒子的软误差弹性。它由如下两个FF数组组成。一个是由冗余FFs组成的阵列，以确定所提出的冗余FFs和常规冗余FFs的辐射硬度。另一种是由传统的d - ff组成的阵列，通过与分接单元的距离来测量SEU(单事件扰动)和MCU(多单元扰动)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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