Minimum power loss for high-side power MOSFETs in DC-DC converter with TBO and high cell density

Abstract

For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds). Two approaches are taken to reduce the Ron.sp & Qgd. First is by shrinking the trench gate width to increase the cell densities up to 645Mcell/inch2 for an ultra low on state resistance using 0.18um design rule process. The other is to obtain lower Qgd with thick bottom oxide (TBO) at minimum trench gate width by double HDP processing. The results shows that the reduce Qgd 36%, total Qg[Vgs=10V] 27% and Qg uniformity around 7% within wafer.