Crossbar architecture based on 2R complementary resistive switching memory cell

Abstract

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.