The FELIN arithmetic coprocessor chip

Abstract

We describe a general VLSI architecture for the computation of arithmetic expressions including floating-point trancendental functions. This architecture is divided in three parts: a communication machine, the control part of a computation machine and the operative part of this computation machine. In order to compute the most usual trancendental functions, we introduced some general algorithms, presented briefly here, including as a particular case the CORDIC scheme. Our major architecture goals were regularity, parametrization and automatic design. The final chip is designed in a 2-Alu CMOS technology, and its name is FELIN (“Fonctions ELémentaires INtégrées is the french for integrated elementary functions”). This work was supported in part by the GRECO C3 and the GCIS of the French CNRS.