A complete power estimation methodology for DSP blocks in FPGAs

Abstract

This work proposes a complete commercial power model for DSP blocks in FPGAs. A pin activities model is developed to estimate the transitions densities at the output of the DSP blocks given the switching activities at the inputs. Such a pin activities model is important in estimating power dissipation during the pre-layout design phase. The power model estimates the total power dissipation in the DSP blocks using the knowledge of all the transitions densities of the inputs and outputs, which are estimated by the proposed pin activities model. The average error of the proposed power model on the design level is less than 2%.