{"title":"FPGA DIGITAL ARCHITECTURE FOR MULTILEVEL SYNCHRONOUS OPTIMAL PULSE WIDTH MODULATION WITH SEAMLESS PULSE PATTERN TRANSITIONS","authors":"J. Lago, Lúcio Steckling, Marcelo Lobo Heldwein","doi":"10.18618/rep.2023.1.0053","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":149812,"journal":{"name":"Eletrônica de Potência","volume":"140 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Eletrônica de Potência","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.18618/rep.2023.1.0053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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