A contention-free Radix-2 8k-point fast Fourier transform engine using single port SRAMs

Abstract

This paper presents a Radix-2 decimation in frequency fast Fourier transform engine that is based on a switch based architecture. The architecture interconnects M processing elements with 2*M memories. An algorithm to eliminate memory access contention is presented. The implementation of an 8192-point FFT with 2 processing elements is presented, including timing and place-and-route results. The length of the FFT can be easily changed to integer powers of 2 from 64 to 8192 points. The switch based architecture provides a factor of M speedup over a single processing element realization. The architecture uses single-port memories and achieves a throughput of roughly 1 GSPS (66% of the throughput of dual-ported SRAM based implementations).