A Design of Versatile Image Processing Platform Based on the Dual Multi-core DSP and FPGA

Zhenhuan Zhan, Wei Hao, Yan Tian, Da-wei Yao, Xianhong Wang
{"title":"A Design of Versatile Image Processing Platform Based on the Dual Multi-core DSP and FPGA","authors":"Zhenhuan Zhan, Wei Hao, Yan Tian, Da-wei Yao, Xianhong Wang","doi":"10.1109/ISCID.2012.210","DOIUrl":null,"url":null,"abstract":"As an application of TI's latest multi-core DSP chip TMS320C6678 and Xilinx's FPGA chip XC5VLX110T, This paper designed and implemented a dual-DSP and FPGA real-time image processing system based on the Serial Rapid IO (SRIO), Hyperlink and reconfigurable technology. It used TMS320C6678 on-chip SRIO and Hyperlink interface module, XC5VLX110T on-chip Rocket IO modules, reconfigurable technology to implement a DSP and FPGA loosely coupled parallel interconnection reconfigurable system. on Embedded operating system's DSP / BIOS architecture, this paper implemented the program of hardware driver of bottom layer and the corresponding data transfer procedures, and also completed the transmission of digital images.","PeriodicalId":246432,"journal":{"name":"2012 Fifth International Symposium on Computational Intelligence and Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Fifth International Symposium on Computational Intelligence and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCID.2012.210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

As an application of TI's latest multi-core DSP chip TMS320C6678 and Xilinx's FPGA chip XC5VLX110T, This paper designed and implemented a dual-DSP and FPGA real-time image processing system based on the Serial Rapid IO (SRIO), Hyperlink and reconfigurable technology. It used TMS320C6678 on-chip SRIO and Hyperlink interface module, XC5VLX110T on-chip Rocket IO modules, reconfigurable technology to implement a DSP and FPGA loosely coupled parallel interconnection reconfigurable system. on Embedded operating system's DSP / BIOS architecture, this paper implemented the program of hardware driver of bottom layer and the corresponding data transfer procedures, and also completed the transmission of digital images.
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基于双多核DSP和FPGA的通用图像处理平台设计
本文应用TI公司最新的多核DSP芯片TMS320C6678和赛灵思公司的FPGA芯片XC5VLX110T,设计并实现了一种基于串行快速IO (SRIO)、Hyperlink和可重构技术的双DSP和FPGA实时图像处理系统。采用TMS320C6678片上SRIO和Hyperlink接口模块、XC5VLX110T片上Rocket IO模块、可重构技术,实现了一个DSP和FPGA松耦合并行互联的可重构系统。本文在嵌入式操作系统的DSP / BIOS架构上,实现了底层硬件驱动程序和相应的数据传输程序,并完成了数字图像的传输。
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