Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture

Abstract

Data intensive applications require massive data transfers between storage and processing units. VLSI scaling has increased the sizes of dynamic memories as well as speeds and capabilities of processing units to a point where, for many such applications, storage and computational processing capabilities are no longer the main limiting factors. Despite this fact, most current architectures fail to meet the performance requirements for such data intensive applications. In this paper, we describe a PIM architecture that harnesses the benefits of VLSI scaling to accelerate matrix operations that constitute the core of many data-intensive applications. We then present data partitioning and placement schemes that are efficient in terms of the computational complexities and internode communication cost. Such approaches are evaluated and analyzed under various computing environments. We also discuss on how to apply such partitioning and placement schemes to each matrix when chains of matrix operations are given as a task.