Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning

Yi-Chen Lu, S. Nath, Vishal Khandelwal, S. Lim
{"title":"Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning","authors":"Yi-Chen Lu, S. Nath, Vishal Khandelwal, S. Lim","doi":"10.1109/ICCAD51958.2021.9643435","DOIUrl":null,"url":null,"abstract":"Modern designs are increasingly reliant on physical design (PD) tools to derive full technology scaling benefits of Moore's Law. Designers often perform power, performance, and area (PPA) exploration through parallel PD runs with different tool configurations. Efficient exploration of PPA is mission-critical for chip designers who are working with stringent time-to-market constraints and finite compute resources. Therefore, a framework that can accurately predict a “doomed run” (i.e., will not meet the PPA targets) at early phases of the PD flow can provide a significant productivity boost by enabling early termination of such runs. Multiple QoR metrics can be leveraged to classify successful or doomed PD runs. In this paper, we specifically focus on the aspect of timing, where our goal is to identify the PD runs that cannot achieve end-of-flow timing results by predicting the post-route total negative slack (TNS) values in early PD phases. To achieve our goal, we develop an end-to-end machine learning (ML) framework that performs TNS prediction by modeling PD implementation as a sequential flow. Particularly, our framework leverages graph neural networks (GNNs) to encode netlist graphs extracted from various PD phases, and utilize long short-term memory (LSTM) networks to perform sequential modeling based on the GNN-encoded features. Experimental results on seven industrial designs with 5:2 train/test split ratio demonstrate that our framework predicts post-route TNS values in high fidelity within 5.2% normalized root mean squared error (NRMSE) in early design stages (e.g., placement, CTS) on the two validation designs that are unseen during training.","PeriodicalId":370791,"journal":{"name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD51958.2021.9643435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

Modern designs are increasingly reliant on physical design (PD) tools to derive full technology scaling benefits of Moore's Law. Designers often perform power, performance, and area (PPA) exploration through parallel PD runs with different tool configurations. Efficient exploration of PPA is mission-critical for chip designers who are working with stringent time-to-market constraints and finite compute resources. Therefore, a framework that can accurately predict a “doomed run” (i.e., will not meet the PPA targets) at early phases of the PD flow can provide a significant productivity boost by enabling early termination of such runs. Multiple QoR metrics can be leveraged to classify successful or doomed PD runs. In this paper, we specifically focus on the aspect of timing, where our goal is to identify the PD runs that cannot achieve end-of-flow timing results by predicting the post-route total negative slack (TNS) values in early PD phases. To achieve our goal, we develop an end-to-end machine learning (ML) framework that performs TNS prediction by modeling PD implementation as a sequential flow. Particularly, our framework leverages graph neural networks (GNNs) to encode netlist graphs extracted from various PD phases, and utilize long short-term memory (LSTM) networks to perform sequential modeling based on the GNN-encoded features. Experimental results on seven industrial designs with 5:2 train/test split ratio demonstrate that our framework predicts post-route TNS values in high fidelity within 5.2% normalized root mean squared error (NRMSE) in early design stages (e.g., placement, CTS) on the two validation designs that are unseen during training.
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利用顺序流和图学习的物理设计中注定运行预测
现代设计越来越依赖于物理设计(PD)工具来获得摩尔定律的全面技术扩展优势。设计人员通常通过使用不同工具配置的并行PD运行来进行功率、性能和面积(PPA)探索。对于面临严格的上市时间限制和有限的计算资源的芯片设计人员来说,高效地探索PPA至关重要。因此,能够在PD流的早期阶段准确预测“注定要失败的运行”(即,将不满足PPA目标)的框架可以通过支持早期终止此类运行来显著提高生产率。可以利用多个QoR指标对成功或失败的PD运行进行分类。在本文中,我们特别关注时序方面,我们的目标是通过预测PD早期阶段的路径后总负松弛(TNS)值来识别无法实现流末时序结果的PD运行。为了实现我们的目标,我们开发了一个端到端机器学习(ML)框架,该框架通过将PD实现建模为顺序流来执行TNS预测。特别是,我们的框架利用图神经网络(gnn)来编码从各个PD阶段提取的网表图,并利用长短期记忆(LSTM)网络来执行基于gnn编码特征的顺序建模。在七个训练/测试分割比为5:2的工业设计上的实验结果表明,我们的框架在训练期间未见的两个验证设计的早期设计阶段(例如,放置,CTS)以5.2%的标准化均方根误差(NRMSE)高保真度预测路线后TNS值。
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