{"title":"An accelerated variable stage size carry skip adder realization using 1s1r resistive memory","authors":"","doi":"10.1142/s0219622023500414","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":257183,"journal":{"name":"International Journal of Information Technology & Decision Making","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Information Technology & Decision Making","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1142/s0219622023500414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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