Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication

Abstract

Achieving lightning fast speed data communication in Chip Multi Processor (CMP) based systems as well as Networkon Chips (NoCs) is always desired for target performance. Data communication links inside the communication fabric of CMP or NoC architectures have strong impact on their performance and power dissipation. Several approaches exist to reduce power dissipation of parallel link on-chip interconnects, a very few techniques are reported for power reduction in serial links. The existing serial-link power reduction techniques don't necessarily account correlation exhibited in the data and hence are limited in terms of accuracy. In this paper, a novel data encoding scheme isproposed for serial links to decrease the number of self transitions to reduce the power in data transmission. The proposed scheme accounts the correlations in the data and hence is more effective for real-life applications. The system architecture as well as the encoding and decoding schemes have been implemented to explore the proposed algorithm applicable for any CMP or NoC architectures. The proposed encoding scheme has been analyzed with various types of real-life data streams. Experimental resultsshow that up to 27% reduction in power dissipation is possible in NoC links by the proposed scheme.