An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors

Abstract

Technology scaling has led to a tremendous increase in the packing density of transistors. However, these small transistors are susceptible to certain impediments that were not present earlier. Manufacturability suffers due to trailing lithography technology which does not scale well with transistor technology. Increased leakage current has reduced effectiveness of burn-in tests. Infant mortality cannot therefore, be completely kept under check. Even during operation, reliability is affected due to CMOS wear-out mechanisms such as time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI), electro migration (EM), and stress induced voiding (SIV).