Verification tool for systolic array design

Abstract

The axiomatization of STA (systolic temporal arithmetic) defines rules for the systolic array in the language of the predicate calculus. The STA formalism is briefly reviewed and an automated verifier is constructed using Prolog. The verification tool is developed to produce a sound and efficient verification process and to provide short-cuts to justify systolic array designs. The STA specifications and the corresponding Prolog programs can be written using an almost identical notation.<>