Reconfigurable Array for Analog Applications

Ziyi Chen, I. Savidis
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Abstract

In this paper, a novel field-programmable analog array (FPAA) fabric consisting of a 6x6 matrix of configurable analog blocks (CABs) is proposed. The implementation of programmable CABs eliminates the use of fixed analog sub-circuits. A unique routing strategy is developed within the CAB units that supports both differential and single-ended mode circuit configurations. The bandwidth limitation due to the routing switches of each individual CAB unit is compensated for through the use of a switch-less routing network between CABs. Algorithms and methodologies are developed to facilitate rapid implementation of analog circuits on the FPAA. The proposed FPAA fabric provides high operating speeds as compared to existing FPAA topologies, while providing greater configuration in the CAB units as compared to switch-less FPAAs. The FPAA core includes 498 programming switches and 14 global switchless interconnects, while occupying an area of 0.1 mm2 in a 65 nm CMOS process. The characteristic power consumption is approximately 24.6 mW for a supply voltage of 1.2 V. Circuits implemented on the proposed FPAA fabric include operational amplifiers (op amps), filters, oscillators, and frequency dividers. The reconfigured bandpass filter provides a center frequency of approximately 1.5 GHz, while the synthesized ring-oscillator and frequency divider support operating frequencies of up to 500 MHz.
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用于模拟应用的可重构阵列
本文提出了一种新型的现场可编程模拟阵列(FPAA)结构,该结构由6x6可配置模拟块(cab)矩阵组成。可编程cab的实现消除了固定模拟子电路的使用。在CAB单元内开发了一种独特的路由策略,支持差分和单端模式电路配置。由于每个单独的CAB单元的路由开关的带宽限制是通过在CAB之间使用无开关路由网络来补偿的。算法和方法的发展,以促进快速实现模拟电路在FPAA。与现有的FPAA拓扑结构相比,拟议的FPAA结构提供了更高的运行速度,同时与无开关FPAA相比,在CAB单元中提供了更大的配置。FPAA核心包括498个编程开关和14个全局无开关互连,而在65纳米CMOS工艺中占地0.1 mm2。电源电压为1.2 V时,特性功耗约为24.6 mW。在提议的FPAA结构上实现的电路包括运算放大器(运放)、滤波器、振荡器和分频器。重新配置的带通滤波器提供约1.5 GHz的中心频率,而合成的环形振荡器和分频器支持高达500 MHz的工作频率。
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