{"title":"The concept of a microcontroller with neural-matrix coprocessor for control systems that exploits reconfigurable FPGAs","authors":"A. Rybarczyk, Michd Szulc","doi":"10.1109/ROMOCO.2002.1177096","DOIUrl":null,"url":null,"abstract":"The new digital architecture of specialized microcontroller with neural coprocessor for efficient real time control systems of robots is presented. The main idea of the paper is to present the on-chip integrated core of the popular microcontroller, program and data memories and the neural-matrix coprocessor. In order to explain the design, the main processor, neural coprocessor and accompanied networks are described. The reconfigurable FPGA matrix has been used as the prototyping platform. It made possible the fast prototyping process. The paper describes also the future work to implement the presented system as ASIC chip.","PeriodicalId":213750,"journal":{"name":"Proceedings of the Third International Workshop on Robot Motion and Control, 2002. RoMoCo '02.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third International Workshop on Robot Motion and Control, 2002. RoMoCo '02.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ROMOCO.2002.1177096","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The new digital architecture of specialized microcontroller with neural coprocessor for efficient real time control systems of robots is presented. The main idea of the paper is to present the on-chip integrated core of the popular microcontroller, program and data memories and the neural-matrix coprocessor. In order to explain the design, the main processor, neural coprocessor and accompanied networks are described. The reconfigurable FPGA matrix has been used as the prototyping platform. It made possible the fast prototyping process. The paper describes also the future work to implement the presented system as ASIC chip.