Automatic Formal Verification of Digital Components of IoTs Using CBMC

Abstract

These days, internet of things (IoT) are being widely used in many safety-critical domains, like healthcare and transportation. Thus, their functional correctness is very important. However, simulation based analysis is based on sampling methods and thus their results are not complete and cannot be termed as accurate. Formal verification has been recently proposed to verify the digital components of IoT devices and thus overcome the incompleteness issues of simulation. However, formal verification process requires manual development of a formal model of the given circuit and its desired properties. Moreover, the verification of the relationship between the formally specified model and its properties sometimes also requires manual interventions. These manual efforts can be quite cumbersome while verifying large systems and thus make formal verification of IoT devices somewhat infeasible for industrial usage. To overcome these limitations, we present a tool chain to automatically formally verify digital components of IoT devices, which are usually expressed in the Verilog language. The proposed methodology primarily leverages upon the strong verification support for the C language. The idea is to convert the given Verilog code and its properties to C language and use bounded model checking to verify the obtained C code. The formally verified C code is then converted back to Verilog to facilitate circuit design steps i.e., synthesis, timing analysis etc., and thus continue with the regular digital system design flow. For illustration, we present the verification of several widely used components of IoT devices, including an ALU and a 64-bit processor, which are fairly complex and to the best of our knowledge have never been formally verified automatically before.