{"title":"A 168 dB high gain folded cascode operational amplifier for Delta-Sigma ADC","authors":"Jing Kai, Yu Ningmei, Quan Xing","doi":"10.1109/ICIEA.2019.8834023","DOIUrl":null,"url":null,"abstract":"A fully differential CMOS folded cascode operational amplifier is presented. It uses gain boosting technique on both NMOS and PMOS branch to enhance total gain. New current-sink topology is used to maximally enhance the open-loop gain as well as not to deteriorate the output swing badly. Local small area but good-performance CT-CMFB is adopted in gain-boosted auxiliary amplifier to optimize both area cost and calibration performance. An improved SC-CMFB is used on total amplifier output to stabilize the output common mode node voltage as well as not to impact differential gain performance. Designed in low-cost UMC 110 nm process with a 5V supply voltage, simulation results show DC gain of 164.1 dB and a phase margin of 63 degree at a unity gain bandwidth of 17.09 MHz. The static current is 174 uA along with achieved PSRR of 186.5dB, making it suitable in high-performance Delta-Sigma ADCs.","PeriodicalId":311302,"journal":{"name":"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2019.8834023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A fully differential CMOS folded cascode operational amplifier is presented. It uses gain boosting technique on both NMOS and PMOS branch to enhance total gain. New current-sink topology is used to maximally enhance the open-loop gain as well as not to deteriorate the output swing badly. Local small area but good-performance CT-CMFB is adopted in gain-boosted auxiliary amplifier to optimize both area cost and calibration performance. An improved SC-CMFB is used on total amplifier output to stabilize the output common mode node voltage as well as not to impact differential gain performance. Designed in low-cost UMC 110 nm process with a 5V supply voltage, simulation results show DC gain of 164.1 dB and a phase margin of 63 degree at a unity gain bandwidth of 17.09 MHz. The static current is 174 uA along with achieved PSRR of 186.5dB, making it suitable in high-performance Delta-Sigma ADCs.