Design and Implementation of the TPM Chip J3210

Abstract

During these years, computer security is in expeditious progressing. With the serious risk of security, the idea of Trusted Computing was introduced to the Information Technology industry. Trusted Computing has to ensure the computing is on the trusted platforms, so the technology of Trusted Computing Platform (TCP) was developed. In the specification of Trusted Computing Group (TCG), Trusted Platform Module (TPM) can be used to ensure that each computer will report its configuration parameters in a trustworthy manner. The cryptographic operations are all taking place in TPM, such as the measurement of Operation System, the encryption process, and the process of personal identification. These kinds of operations need huge computing power. Besides, these operations have to be done in TPM totally under the consideration of security. It is obviously a TPM chip should offer sufficient computing power to do these kinds of operations; otherwise the performance of trusted computing would descend seriously. In this paper, a high performance TPM chip J3210 based on SPARC v8 is designed and implemented. This high performance TPM chip J3210 consists of a high performance RISC CPU, a RSA/ECC cryptographic acceleration engine, a hash engine, a symmetric cryptographic acceleration engine, a random number generator and some peripheral interfaces. These internal Intellectual Property (IP) cores are elaborately designed and carefully configured. As a result, it demonstrates a high performance of cryptographic operations.