S. J. de Mesquita, F. Antunes, S. Daher, R. Bascopé
{"title":"An aiding tool to the design and simulation of multilevel inverters","authors":"S. J. de Mesquita, F. Antunes, S. Daher, R. Bascopé","doi":"10.1109/COBEP.2017.8257353","DOIUrl":null,"url":null,"abstract":"This paper presents a new support aiding tool for the design of multilevel-inverter, through simulation analysis by using Orcad Pspice. The new proposed software generates programmable pulses in accordance to the operation principle of a desired topology. It will be also presented several simulated inverters using the software. This new resource enables the fine-tuning of dead time between complementary switches of a same leg. This is done through programming, applying semiconductor technology prior knowledge. It also provides a portable code which facilitates its implementation in a microcontroller, FPGA or DSP. A test case using a 81 level output voltage cascade multilevel inverter is presented to show the performance of the proposed software tool.","PeriodicalId":375493,"journal":{"name":"2017 Brazilian Power Electronics Conference (COBEP)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Brazilian Power Electronics Conference (COBEP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COBEP.2017.8257353","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a new support aiding tool for the design of multilevel-inverter, through simulation analysis by using Orcad Pspice. The new proposed software generates programmable pulses in accordance to the operation principle of a desired topology. It will be also presented several simulated inverters using the software. This new resource enables the fine-tuning of dead time between complementary switches of a same leg. This is done through programming, applying semiconductor technology prior knowledge. It also provides a portable code which facilitates its implementation in a microcontroller, FPGA or DSP. A test case using a 81 level output voltage cascade multilevel inverter is presented to show the performance of the proposed software tool.