A Novel NW-TFET Based Low Power, High Speed and Variations Resistant Comparator with Improved Linearity

2022 1st International Conference on the Paradigm Shifts in Communication, Embedded Systems, Machine Learning and Signal Processing (PCEMS) Pub Date : 2022-05-06 DOI:10.1109/PCEMS55161.2022.9807858

Chithraja Rajan, Jyoti Patel, V. Satpute, D. P. Samajdar

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引用次数: 1

Abstract

This paper focuses on Hetero-Junction Nanowire TFET (HJ-NW-TFET) based circuit implementation. Here, a combination of an electrically doped drain, physically doped source and hetero materials form a HJ that provide better ON current and low ambipolarity in NW-TFET. Formerly, only device electrical characteristics are imported in circuit through Verilog-A modeling and least has been investigated regarding linearity and reliability. Whereas, physical variations incorporated during fabrication and environmental changes are two serious sources of design deviations which can neither be eliminated nor can be predicated as they are inherited and unique in nature. Therefore, to check the device performance in various situations a lookup table based low power comparator is implemented using HJ-NW-TFET. Comparator designed in this way has 10 ns delay even in low supply voltage and the effect of 10 % variations on HJ-NW-TFET performance is less than 5 % which promises distortion free and fault tolerant real circuit applications.

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一种新型的NW-TFET低功率、高速度、耐变化线性比较器

本文主要研究基于异质结纳米线TFET (HJ-NW-TFET)的电路实现。在这里，电掺杂漏极、物理掺杂源和异质材料的组合形成HJ，在NW-TFET中提供更好的ON电流和低双极性。以往仅通过Verilog-A建模在电路中导入器件电气特性，对线性度和可靠性的研究较少。然而，在制造过程中包含的物理变化和环境变化是设计偏差的两个严重来源，既不能消除也不能预测，因为它们是遗传的和独特的性质。因此，为了检查器件在各种情况下的性能，采用HJ-NW-TFET实现了基于查找表的低功耗比较器。用这种方法设计的比较器即使在低电源电压下也有10ns的延迟，并且10%的变化对HJ-NW-TFET性能的影响小于5%，保证了无失真和容错的实际电路应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 1st International Conference on the Paradigm Shifts in Communication, Embedded Systems, Machine Learning and Signal Processing (PCEMS)

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