Development and Analysis of In GaAs Nanowire Junctionless MOSFET with 10 nm gate length

Abstract

The device performance of nanowire junctionless MOSFET (NW-JL-MOSFET) with InGaAs as core material in the sub-10 nm regime is examined by a device simulator, namely ATLAS. The focus is on gate-all-around nanowires with InGaAs core. These devices are further examined by adding gate-stack (high-k dielectric + oxide) method. It is observed that optimal selection of structure parameters of InGaAs NW-JL-MOSFET attains higher drain current and optimal performance. This proposed architecture also provides better switching speed of the structure. The gate dielectric material optimization of the structure is attained via broad device simulation. In this manuscript, a literature is carried for the short channel effects like subthreshold swing, Ion/Ioff ratio, Threshold voltage and drain induced barrier lowering (DIBL). The InGaAs device has a better threshold voltage and Ion/Ioff ratio, according to simulation data.