Segmentation of Integrated Circuit Layouts from Scan Electron Microscopy Images

Abstract

One of the most important steps in the extraction of layout for reverse engineering of the integrated circuits (ICs) is the image segmentation of wires and vias from scan electron microscope (SEM) images. This segmentation is challenging due to the gigabytes of image data just for a single IC, image noise, and artefacts. Existing approaches rely on image intensity threshold-based methods but requires significant amount of manual user interactions to correct errors in segmentation. In this paper, we describe an image processing pipeline for segmenting IC layouts from SEM images. Our pipeline includes image normalization, image preprocessing, and segmentation. The segmentation results were compared using a custom-built comparison tool. The results showed, with the correct filters/methods selection, an increase in accuracy of the segmentation for all tested image sets.