Low-Leakage ESD Structures in 130nm CMOS Technology

Abstract

The paper addresses a non-standard ESD protection structures developed in general purpose 130 nm CMOS technology and modeled in VerilogA language for transistor-level circuit simulators. ESD structures represent an additional load to the on-chip circuits and can exhibit quite significant portion of the overall power consumption in low-voltage and low-power circuit designs. We describe and discuss the properties of ESD structures designed with minimized leakage current as the main design constraint, while still maintaining their protection capabilities. The other ESD structure discussed in this article was designed for negative voltage levels, which brings completely new possibilities in terms of the power supply voltage range and circuit design. The accuracy of developed VerilogA models is compared to experimental data obtained by laboratory measurement at room temperature and compact models provided by the foundry.