A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI:10.1109/ASPDAC.2011.5722293

Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng

引用次数: 0

Abstract

An energy-efficient programmable LDPC decoder is proposed for WiMax and Wi-Fi applications. The proposed decoder is designed with overlapped processing units, flexible message passing network and medium-grain partitioned memories to achieve flexibility, area reduction, and energy efficiency. The decoder can be programmed by host processor with several special-purpose micro-instructions. Thus, various operation modes can be reconfigured. Fabricated in SMIC 0.13μm 1P8M CMOS process, the chip occupies 4.32 mm2 with core area 2.97 mm2, and consumes 170mW with a throughput of 302Mb/s when operating at 145MHz and 1.2V.

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4.32 mm2 170mW LDPC解码器，0.13μm CMOS，适用于WiMax/Wi-Fi应用

提出了一种适用于WiMax和Wi-Fi应用的节能可编程LDPC解码器。本文提出的解码器采用重叠处理单元、灵活的消息传递网络和中粒分区存储器设计，以实现灵活性、减少面积和节能。该解码器可由主处理器编写若干专用微指令。因此，可以重新配置各种操作模式。该芯片采用中芯国际0.13μm 1P8M CMOS工艺制造，芯片占地4.32 mm2，核心面积2.97 mm2，功耗170mW，工作在145MHz和1.2V时的吞吐量为302Mb/s。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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