Analysis and design of virtual ESR circuit with constant on time control

Abstract

For a constant on time controller to be stable with all ceramic output capacitance, a virtual ESR (Equivalent Series Resistance) circuit is needed to inject the required ripple voltage into the FB (Feedback) node. This paper proposes a new stability criterion, which is that the FB node ripple voltage need to have the same phase as the inductor current and have certain amplitude to filter out noise. Based on this stability criterion, the virtual ESR circuit is analyzed. The contributions from the phase node voltage, the inductor current and the output voltage are derived with superposition. Two methods to design the virtual ESR circuit, the In Phase Dominance Method and the Phase Cancellation Method, are proposed and experimentally verified. Comparisons between real ESR and the virtual ESR are made. The effects of virtual ESR circuit on load transient responses, power saving mode waveforms and output voltage setting are also discussed.