Design of an improved bandgap reference in 180nm CMOS process technology

R. Akshaya, Sivaganesan Siva
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引用次数: 8

Abstract

This paper grants implementation and design of Bandgap reference circuit with 0.2ppm/ low temperature coefficient in 180nm CMOS process technology. The designed circuit achieves a simulated output voltage reference of 1.12V at room temperature (27°C) with the temperature range of −40°C to +125°C under supply voltage of 1.8V. The power consumption is 52.37uW at room temperature and active area is 81.4um∗63.43um. The designed circuit was implemented using Cadence Virtuoso and simulated using Spectre ADE.
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基于180nm CMOS工艺技术的带隙改进参考设计
本文给出了在180nm CMOS工艺中低温系数为0.2ppm/的带隙参考电路的实现与设计。本设计电路在室温(27℃)下实现了1.12V的模拟输出基准电压,温度范围为- 40℃~ +125℃,电源电压为1.8V。室温下功耗为52.37uW,有效面积为81.4um * 63.43um。设计的电路使用Cadence Virtuoso实现,并使用Spectre ADE进行仿真。
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