{"title":"An analog floating-gate memory in a standard digital technology","authors":"T. Lande, H. Ranjbar, M. Ismail, Y. Berg","doi":"10.1109/MNNFS.1996.493802","DOIUrl":null,"url":null,"abstract":"In this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based on a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the memory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results from test chips fabricated in a standard 2-micron CMOS process show six orders of magnitude dynamic range in current for subthreshold operation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493802","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
In this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based on a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the memory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results from test chips fabricated in a standard 2-micron CMOS process show six orders of magnitude dynamic range in current for subthreshold operation.