MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2015-07-19 DOI:10.1109/SAMOS.2015.7363704

P. Wehner, J. Rettkowski, Tobias Kleinschmidt, D. Göhringer

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引用次数: 19

Abstract

In this paper a SystemC simulator for Network-on-Chip (NoC) based Multiprocessor Systems-on-Chip (MPSoCs) is presented. The simulator currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First and an adaptive West-First algorithm. The impact of routing algorithms regarding performance can be analyzed by means of the presented simulator. In order to simulate a heterogeneous MPSoC, ARM processors and MicroBlazes can be attached to the NoC. Processor and peripheral models used within the test platforms are provided by Imperas/OVP. Moreover, traffic generators are available to analyze the system. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator multiple platforms and applications were put under test and compared with a hardware implementation. The comparison shows that the simulator improves the development of MPSoCs by early estimation of system requirements.

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MPSoCSim:一个扩展的OVP模拟器，用于基于片上网络的异构mpsoc的建模和评估

本文介绍了一种基于片上网络(NoC)的多处理器片上系统(mpsoc)的SystemC模拟器。该模拟器目前支持网格拓扑与虫洞交换和几种路由算法，如XY-，一个最小的西优先和自适应西优先算法。利用所设计的仿真器可以分析路由算法对性能的影响。为了模拟异构MPSoC, ARM处理器和microblaze可以附加到NoC上。测试平台中使用的处理器和外设模型由Imperas/OVP提供。此外，还可以使用流量生成器对系统进行分析。一个额外的SystemC组件可以从应用程序中读出模拟时间。为了对模拟器进行评估，对多个平台和应用进行了测试，并与硬件实现进行了比较。仿真结果表明，该仿真器通过对系统需求的早期估计，提高了mpsoc的开发效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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