Delay Estimation of MOSFET- and FINFET-based Hybrid Adders

Abstract

Speed is an integral part of circuit designing. Conventional CMOS (C-CMOS) is one of the widely used logic style; however, it has the disadvantage of producing greater delay. Several alternatives have been proposed. One such alternative is the hybrid adders that provide better performance in terms of delay. Various hybrid adders have been proposed, for instance Transmission gate full adders (TGA) and Hybrid pass logic with static CMOS output drive (New HPSC), that provide different delays. In this research work, the performance comparison analysis of different adders is presented by observing its propagation delay and transistor count. The C-CMOS, TGA and New HPSC full adders were considered for the performance comparison. The circuits have been implemented in FINFET model with 32nm technology node and in MOSFET model with 180nm technology node. The circuit implementation and analysis are performed using Cadence® Virtuoso tool. Simulation results reveal that TGA is relatively faster and requires minimum hardware than the other adders