Development of Block-Cipher Library for Reconfigurable Computers

Miaoqing Huang, T. El-Ghazawi, B. Larson, K. Gaj
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引用次数: 2

Abstract

Reconfigurable computing is gaining rising attention as an alternative to traditional processing for many applications. Data encryption and decryption is one of these applications, which can get tremendous speedup running on FPGAs instead of microprocessors. We have developed a block-cipher library that covers 15 most popular encryption algorithms, and generated 35 bitstreams running on the SGI's latest version of a reconfigurable computer, RASCRC-100. The end- to-end throughput of 1.136 GB/s have been demonstrated for almost all ciphers, and was limited only by the input/output interface, rather than the FPGA processing time. The library is written in Verilog-HDL, and can be easily ported to other reconfigurable computing platforms. It provides means for cryptographers and computer scientists to program reconfigurable computers without the need for detailed knowledge of hardware design.
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可重构计算机分组密码库的开发
在许多应用中,可重构计算作为传统处理的一种替代方案正获得越来越多的关注。数据加密和解密就是其中一种应用,它可以在fpga上而不是微处理器上获得巨大的速度提升。我们开发了一个分组密码库,涵盖了15种最流行的加密算法,并在SGI最新版本的可重构计算机RASCRC-100上生成了35个比特流。对于几乎所有的密码,已经证明了1.136 GB/s的端到端吞吐量,并且仅受输入/输出接口的限制,而不受FPGA处理时间的限制。该库是用Verilog-HDL编写的,可以很容易地移植到其他可重构的计算平台上。它为密码学家和计算机科学家提供了在不需要详细的硬件设计知识的情况下编写可重构计算机的方法。
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